This invention relates to the manufacture of advanced semiconductor devices, particularly advanced CMOS integrated devices in which metal gate electrodes are used. With the continued scaling of CMOS devices to smaller dimensions, the gate dielectrics of these devices have been reduced to thicknesses well below 20 Å. This in turn has led to greatly increased gate leakage currents and diffusion of dopants from the polysilicon gate structures (often referred to as the poly depletion effect). Alternatives to doped polysilicon, such as metals and silicides, are now being used in gate structures to mitigate the poly depletion effect and control the leakage current, and thus to ensure electrical performance in highly integrated CMOS devices. A silicide gate is typically formed by a “salicide” process, in which a polysilicon gate having n+ and p+ areas is covered with a layer of silicide-forming metal (e.g. Co) and then converted to a metal silicide.
FIGS. 1A–1C are schematic illustrations of a typical polysilicon gate structure. FIG. 1A is a plan view of structure 10, which includes n+ polysilicon gate 11 and p+ polysilicon gate 12. As shown in FIG. 1A, the n+ and p+ regions are in contact; this structure is typically found in SRAM devices. The top surface of the gate structure is generally covered with a hardmask (typically nitride) 17. A nitride etch stop layer 13 and HDP oxide 14 have been deposited over the gate regions. (Oxide region 14 is preferably HDP oxide rather than BPSG, in order to permit processing at lower temperatures.) FIG. 1B is a longitudinal cross-section view, showing that the gate regions 11, 12 are formed on a gate oxide layer 15 overlying substrate 1. FIG. 1C is a transverse cross-section view, showing nitride spacers 16, the nitride etch stop layer 13 and HDP oxide 14 on either side of the polysilicon gate. Conversion of the gate structure to a silicide involves removing the etch stop 13 and hardmask 17 from the top of the gate, then depositing a layer 18 of silicide-forming metal on the polysilicon (see FIG. 2A). A salicide process is then performed (details of which are known in the art) to convert the respective polysilicon regions 11, 12 to a silicide layer having regions 19a, 19b (FIG. 2B).
The difference in doping between polysilicon regions 11 and 12 leads to formation of silicide regions of different composition; for example, CoxSiy in region 19a, CowSiz in region 19b. This in turn leads to formation of a high-resistivity region near the interface between regions 19a and 19b. In addition, it is desirable to provide different stresses for gate regions 19a and 19b (which will become NFET and PFET gates respectively). Accordingly, there is a need for a silicide-gate process in which the polysilicon gate regions are separately converted to a silicide, as opposed to conversion simultaneously using a blanket metal layer.